1. Field of the Invention
The present invention relates to a semiconductor memory device and a method of manufacturing the device, and particularly, to a pattern layout of a high-integration and large-capacity dynamic RAM (random access read/write memory).
2. Description of the Related Art
The degree of integration and the size of dynamic RAMs have increased as much as four times in the last three years. In accordance with such size increase, the structure in which a capacitor is formed within a trench for the purpose of integrating a capacitor having a sufficient capacity within a small area, has been proposed. An example of the device having such a structure is a dynamic RAM having a HSPC (half-Vcc sheath-plate capacitor) discussed in IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 35, NO. 8, 1988, P.1257.
FIG. 1 is a plan view showing a layout of the main layer of a conventional semiconductor memory device. FIGS. 2 to 4 illustrate a method of manufacturing the conventional semiconductor memory device. FIG. 2 illustrates the first step, and is a cross section of the section taken along the line 2--2 in FIG. 1, after the completion of the first step. FIG. 3 illustrates the first step, and is a cross section of the section taken along the line 3--3 in FIG. 1, after the completion of the first step. FIG. 4 illustrates the second step, and is a cross section of the section taken along the line 4--4 in FIG. 1, after the completion of the second step.
First, as shown in FIGS. 2 and 3, an element separation oxide film 3a is formed on the surface of a P-type silicon substrate 1 by the LOCOS (local oxidation of silicon) method using a mask 2b having the element separation pattern 2a.
More specifically, a silicon nitride film (not shown) is formed on the surface of a P-type silicon substrate 1, and the silicon nitride film is etched using the mask 2b having the element separation pattern 2a. Next, the surface of the portion of the P-type silicon substrate 1, which is exposed by the etching, is thermally oxidized, thus forming an element separation oxide film 3a. In this case, the transfer error between the mask 2b having the element separation pattern 2a and the element separation oxide film 3a varies in accordance with the pattern shape of the element separation oxide film 3a. In detail, the transfer error .DELTA.L.sub.1 with regard to the element separation oxide film 3a shown in FIG. 2 is larger than the conversion error .DELTA.L.sub.2 with regard to the element separation oxide film 3a shown in FIG. 3.
After that, the silicon nitride film is removed, and a sheath plate capacitor (HSPC) 11 is formed on a P-type silicon substrate 1 as shown in FIG. 4 by the method described in IEEE TRANSACTIONS ON ELECTRON DEVICES.
More specifically, a trench 5 having a depth of about 3 .mu.m is formed on the P-type silicon substrate 1 by use of a mask (not shown) corresponding to a trench pattern 4a shown in FIG. 1. During the formation, the trench 5 goes through a part of the element separation oxide film 3a. Next, a SiO.sub.2 film 6 is formed on only a side wall of the trench 5. Then, a diffusion layer plate 7 is formed on a bottom portion of the trench 5, and a plate electrode 8 made by processing polysilicon into a sheath shape, is formed in the trench 5. After that, a capacitor insulation film 9 is formed in and on the plate electrode 8. Subsequently, the trench 5 is filled with polysilicon, and a storage node electrode 10 is formed in the trench 5. Thus, a sheath plate capacitor 11 consisting of the plate electrode 8, capacitor insulation film 9 and storage node electrode 10, is formed.
An oxide film 12 is formed selectively on the storage node electrode 10, and a gate insulation film 13 is formed on the surface of the P-type silicon substrate 1.
A polysilicon film 14a is deposited on the gate insulation film 13, the oxide film 12 and the element separation oxide film 3a. A resist 15a is applied on the polysilicon film 14a. After that, the resist 15a is patterned by a mask 16a corresponding to a word line pattern 16 shown in FIG. 1, a resist pattern 15 is formed on the polysilicon film 14a. The polysilicon film 14a is etched with the resist pattern 15 serving as a mask, thus forming a gate electrode 14 made of the polysilicon film 14a. Next, an ion implantation is carried out using the gate electrode 14 as a mask, and therefore a diffusion layer 17 of the source-drain region is formed on the P-type silicon substrate 1.
The resist pattern 15 is removed, and bit lines and a wiring portion are formed, thus completing a dynamic RAM.
According to the conventional semiconductor memory device and the manufacturing method thereof, the element separation oxide film 3a is formed on the surface of the P-type silicon substrate 1 with the mask 2b having the element separation pattern 2a shown in FIG. 1. In accordance with the shape of the element separation oxide film 3a, the transfer error between the element separation oxide film 3a and the mask 2b varies, as indicated by .DELTA.L.sub.1 and .DELTA.L.sub.2. More specifically, the transfer error .DELTA.L.sub.1 indicated by the cross section of the element separation oxide film 3a taken along the line 2--2 of FIG. 1 differs from the transfer error .DELTA.L.sub.2 indicated by the cross section taken along the line 3--3 of FIG. 1, which is vertical to the line 2--2. As a result, the conventional manufacturing method is not appropriate for the downsizing of devices, and the controllability of the manufacturing step is low, thus significantly degrading the yield of the product.
Further, it is difficult to manufacture a phase shift mask of the element separation pattern 2a shown in FIG. 1, and therefore the conventional method is not suitable for minute elements.
Furthermore, as can be seen in FIG. 4, the continuous surface of all of the element separation oxide film 3a, the oxide film 12 and the gate insulation film 13 cannot be flattened. Therefore, a difference in level is created in the portion of the polysilicon film 14a formed on the element separation film 3a, the oxide film 12 and the gate insulation film 13, which is situated on the boundary between the oxide film 12 and the insulation film 13. Consequently, the transfer error .DELTA.L.sub.3 with respect to the mask 16a occurs only in pass word lines 19, such that the pass word lines 19 are made narrower than the designed value. As a result, the performance of the product device may be degraded, i.e. an increase in the wiring results.